1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register with reduced response time.
2. Description of the Prior Art
A liquid crystal display (LCD) is a flat panel display fabricated on a glass substrate. To reduce the manufacturing cost, fabricating driving control circuits on the glass substrate has become a trend. In most cases, the driving control circuits are composed of thin film transistors (TFTs) using amorphous silicon, for example, as their semiconductor layer.
FIG. 1 illustrates a diagram of a conventional LCD 100. FIG. 2 illustrates a diagram of a gate driving circuit 120 of the LCD 100 of FIG. 1. FIG. 3 illustrates a diagram of a shift register 122 of the gate driving circuit 120 of FIG. 2. As shown in FIG. 1, the LCD 100 includes a display array 110, a control circuit 124, and a gate driving circuit 120. The display array 110 is utilized for displaying images. The control circuit 124 is utilized for generating signals, such as a first clock signal CK, a second clock signal XCK, and a start signal ST, required by the gate driving circuit 120 during operation, as shown in FIG. 2. The gate driving circuit 120 is utilized for driving the display array 110.
As illustrated in FIG. 2, the gate driving circuit 120 includes a plurality of shift registers 122. The shift registers 122 are coupled in a cascade. For each shift register 122, a corresponding gate signal GOUT is generated for sequentially driving the display array 110 in response to the first clock signal CK and the second clock signal XCK. The phase of the second clock signal XCK is generally opposite to the phase of the first clock signal CK. Each shift register 122 has an output end OUT, an input end IN, and a feedback end FB.
As illustrated in FIG. 3, the shift register 122 includes a signal generating circuit 310, a driving circuit 320, a reset circuit 330, and a control switch 340. The signal generating circuit 310 includes a switch TFT7, which can be realized with a thin film transistor, for generating a gate signal GOUT(N) at the output end OUT of the shift register 122 in response to the first clock signal CK while the signal generating circuit 310 is turned on. Note that the gate signal GOUT(N) can also be generated in response to the second clock signal XCK. The driving circuit 320 is utilized for controlling the signal generating circuit 310 in response to the input signal received by the input end IN of the shift register 122. The input signal received by the input end IN of the shift register 122 is a gate signal GOUT(N−1) from the shift register 122 of the previous stage or the start signal ST. The reset circuit 330 is utilized for turning off the signal generating circuit 310 and for resetting the gate signal GOUT(N) outputted from the output end OUT. Specifically, the voltage of the output end is lowered to a predetermined voltage VSS by the reset circuit 330. The control switch 340 is utilized for resetting the gate signal GOUT(N) outputted by the output end OUT in response to the feedback signal received by the feedback end FB where the feedback signal received by the feedback end FB is a gate signal GOUT(N+1) from an output end of the shift register of the next stage.
Note that both the control switch 340 and the reset circuit 330 are both utilized for resetting the gate signal GOUT(N) outputted by the output end OUT; however, the control circuit 340 differs from the reset circuit 330 in that the control circuit 340 only operates after receiving a gate signal GOUT(N+1) from the shift register of the next stage. In contrast, the reset circuit 330 operates continuously for a long period of time. If a TFT keeps operating for a long period of time, its efficiency may decrease and its lifespan may be shortened as well. Therefore, in order to prevent the noise interference and prolong the lifespan of the shift register, the control switch 340 operates only once in an operation cycle.
The operation of the conventional shift register 122 is explained in detail with reference to FIGS. 3 and 4. FIG. 4 illustrates a timing diagram of each related signal of the shift register 122 of FIG. 3 during operation. As illustrated in FIG. 4, in the time period T1, the input signal received by the input end IN (i.e., the gate signal GOUT(N−1) from the output end of the shift register of the previous stage or a start signal ST) is raised to be high, thereby initializing a TFT1 of the driving circuit 320, which in turn causes the TFT7 of the signal generating circuit 310 to initialize as well. However, because the first clock signal CK at T1 is low, the gate signal GOUT(N) from the output end OUT remains low. Furthermore, the input signal GOUT(N−1) or the start signal ST initializes a TFT4 of the reset circuit 330 to lower the voltage of the node N2 to be low, and at the same time the reset circuit 330 also stops turning off the signal generating circuit 330. However, the voltage of the node N3 is maintained to be high due to the DC voltage VDD, and thus the reset circuit 330 can reset the gate signal GOUT(N) of the output end OUT so that the gate signal GOUT(N) is lowered to be low. The control switch 340 does not operate because the feedback signal GOUT(N+1) of the feedback end FB is low.
At time period T2, the input signal GOUT(N−1) or start signal ST received by the input end IN is lowered to be low, and thus the TFT1 of the driving circuit 320 is turned off; however, the TFT7 of the signal generating circuit 310 is still turned on, and the voltage at the node N1 is raised to be high due to parasitic capacitance when the first clock signal CK is raised to be high. Meanwhile, the voltage of the output end OUT is also raised to be high. Furthermore, the voltage at node N2 of the reset circuit 330 is low(the second clock signal XCK at T2 is low), so the signal generating circuit 310 is still turned off. The voltage at the node N3 of the reset circuit 330 is lowered to be low (TFT6 is turned on by the gate signal GOUT(N) from the output end OUT), such that the gate signal GOUT(N) from the output end OUT stops resetting. The control switch 340 does not operate because the feedback signal GOUT(N+1) of the feedback end FB is low.
At time period T3, when the feedback signal GOUT(N+1) of the feedback end FB rises to be high, TFT9 of the control switch 340 is turned on and the gate signal GOUT(N) from the output end OUT is lowered to be low. Furthermore, the reset circuit 330 rises to be high in response to the second clock signal XCK while TFT2 is turned on. As a result, TFT7 of the signal generating circuit 310 is turned off. The reset circuit 330 also rises to be high at node N3 and resets the gate signal GOUT(N) outputted from the output end OUT again. Also the gate signal GOUT(N) from the output end OUT is lowered to be low.
Within subsequent periods of time, the reset circuit 330 will continue operating to turn off the signal generating circuit 310 and to lower the gate signal GOUT(N) outputted from the output end to be low until the input signal GOUT(N−1) of the input end IN or the start signal ST is again raised to be high. Also, a shift register 122 of the next stage will repeat the above-mentioned operations, so that the gate signal GOUT can be sequentially generated to drive the display array 110.
However, the gate signal GOUT from each stage shift register 122 is not only utilized for driving the display array 110, but also utilized for outputting to an input end IN of a next stage shift register 122 and a feedback end FB of a previous stage shift register 122, and therefore the work load of the output end OUT is increased. This action results in increasing the rising time of the gate signal GOUT from each stage shift register 122. While the rising time of the gate signal GOUT is increased, the feedback signal received by the shift register of the previous stage is weakened, hence increasing the falling time of the gate signal GOUT from the shift register 122 of the previous stage. Therefore, as can be seen, the conventional shift register has an undesired, long response time.